123
XMEGA A [MANUAL]
8077I–AVR–11/2012
Bit 1 – ENABLE: Enable
This bit enables the WDT. Clearing this bit disables the watchdog timer.
In order to change this bit, the CEN bit in “CTRL – Control register” on page 122 must be written to one at the same time.
This bit is protected by the configuration change protection mechanism, For a detailed description, refer to “Configuration
Bit 0 – CEN: Change Enable
This bit enables the ability to change the configuration of the “CTRL – Control register” on page 122. When writing a new
value to this register, this bit must be written to one at the same time for the changes to take effect. This bit is protected
by the configuration change protection mechanism. For a detailed description, refer to “Configuration Change Protection”
11.7.2 WINCTRL – Window Mode Control register
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 5:2 – WPER[3:0]: Window Mode Timeout Period
These bits determine the closed window period as a number of 1kHz ULP oscillator cycles in window mode operation.
The typical different closed window periods are found in Table 11-2. The initial values of these bits are set by the
watchdog window timeout period (WDWP) fuses, and are loaded at power-on. In normal mode these bits are not in use.
In order to change these bits, the WCEN bit must be written to one at the same time. These bits are protected by the
configuration change protection mechanism. For a detailed description, refer to “Configuration Change Protection” on
Table 11-2.
Watchdog closed window periods.
Bit
7
6
5432
1
0
+0x01
WPER[3:0]
WEN
WCEN
Read/Write (unlocked)
R
R/W
Read/Write (locked)
R
RRRR
R/W
Initial Value (x = fuse)
0
X
0
WPER[3:0]
Group configuration
Typical closed window periods
0000
8CLK
8ms
0001
16CLK
16ms
0010
32CLK
32ms
0011
64CLK
64ms
0100
128CLK
0.128s
0101
256CLK
0.256s
0110
512CLK
0.512s
0111
1KCLK
1.0s
1000
2KCLK
2.0s
1001
4KCLK
4.0s
1010
8KCLK
8.0s
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